1. Field of the Invention
This invention relates generally to electronic frequency synthesizer circuits. More particularly, this invention relates to phase locked loop frequency synthesizers. Even more particularly, this invention relates to loop precharge circuits for improving settling time of phase locked loop frequency synthesizers.
2. Description of Related Art
Phase locked loop frequency synthesizers, as shown in FIG. 1, have a voltage controlled oscillator 5 that generates a fundamental output signal ωo 10. A portion of the fundamental output signal ωo 10 is fed back as an input to the feedback divider 15. This portion of the fundamental output signal ωo 10 is divided a factor of N or N+1 to be converted to a frequency approximately equal to the frequency of an input reference signal ωREF 25. The divided fundamental output signal ωo 10 and input reference signal ωREF 25 are the inputs to an error detector 20. The error detector has a phase frequency detector 30 and a charge pump 40. The phase frequency detector 20 compares the frequency and phase of the fundamental output signal ωo 10 and the input reference signal ωREF 25 to develop the an output error signal εs 35. The output error signal εs 35 is an input to the charge pump 40. The charge pump 40 creates a charge current ic 45 that is proportional to the output error signal εs 35. The charge current ic 45 is the input control signal to the loop filter 50. The loop filter 50 filters any spurious signals that may exist in the output error signal εs 35 to generate an essentially DC voltage control signal for the voltage controlled oscillator 5. It is known in the art that the loop filter 50 may take any number of configurations including passive lead/lag networks, active integrators with either passive lead networks or passive lead/lag net works. In the example as shown, the resistor R1, 55, the capacitor C2 60, and the capacitor C1, 65 form a lead/lag network.
It can be shown that the size of the filter capacitor C2 60 determines the time constant for the settling of the DC voltage control signal at initialization of the voltage control oscillator 5 or a change of frequency of the voltage controlled oscillator 5. If the filter capacitor C2 is large the fundamental output signal ωo 10 is stable but has a long time constant at initialization or frequency change of the voltage controlled oscillator 5. On the other hand, if the filter capacitor C2 is small, the fundamental output signal ωo 10 is subject to minor fluctuations and is not as stable. However, the time constant at initialization is short and the voltage controlled oscillator 5 adjusts very quickly either at startup or with frequency changes.
The U3600BM programmable single-chip multichannel cordless telephone integrated circuit from Atmel Corporation, San Jose, Calif. for operation in 900 MHz wireless radio frequency applications employs phase locked loops for the modulator, demodulator, mixer, and local oscillator. The phase locked loops of the mixer and local oscillator must be tunable to select the channels of operation of the cordless telephone application. The voltage controlled oscillator 5 in such an application of the U3600BM has a coarse tuning circuit 70 which adjusts the fundamental output signal ωo 10 to the midband of each channel of the 900 Mhz radio band. The frequency select signal FSEL 75 provides a command signal, generally digital, the forces the voltage controlled oscillator 5 to adjust the fundamental output signal ωo 10 to the midband frequency.
In applications that require rapid changes to the channel setting of the voltage controlled oscillator 5, it is desirable to precharge the loop filter 50 to a middle voltage level representative of the middle range of the output error signal εs 35. The U3600BM includes a loop precharge circuit that is activated when the U3600BM is in receive mode that charges the modulator loop filter to about half of the voltage level of the charge pump 45 voltage level. This precharge insures a fast locking time of the phased locked loop.
The concept of precharging filter circuits is further described in “The TDA 5220 ASK/FSK Single Conversion Receiver—Version 1.1, Infineon Technologies AG, München, Germany, October 2004, pp,: 28–31. The TDA 5220 incorporates a precharge circuit for a loop filter of a slicer threshold. The data slicer threshold is generated with an external RC network. It is necessary to use large values for the capacitor in order to achieve long time constants. When the device is turned on the long time constant dominates the time necessary for the device to be able to demodulate data properly, since the capacitor has been discharged by leakage currents. When the slicer is activated, the loop filter is precharged by an in rush current. This current is then deactivated when the capacitor is charged to middle voltage level value.
“A Simple Precharged CMOS Phase Frequency Detector”, Johansson, IEEE Journal of Solid-State Circuits, February 1998, pp.: 295–299, Volume: 33, Issue: 2, proposes a simple precharged CMOS phase frequency detector (PFD).
U.S. Pat. No. 6,504,437 (Nelson, et al.) describes a phase-lock loop (PLL) circuit provides fast locking and low spurious modulation jitter through “gearshifting” control. The gearshifting PLL combines the advantages of low jitter from integer-N PLL and fast locking from fractional-N PLL. The PLL circuit includes a phase/frequency detector, a charge pump, a loop filter, and a voltage controlled oscillator (VCO). Control of the PLL circuit includes configuring the PLL circuit in two configurations, one for each phase of operation. The bandwidth of the loop filter is increased during the first phase of operation and the circuit is locked to a frequency that is close to the desired output frequency. During the second phase, the bandwidth of the loop filter is decreased and the circuit is locked to the desired frequency. The first configuration provides a relatively fast lock time compared to the lock time provided by the second configuration. The second configuration provides more stability than the first configuration.